1. Field of the Invention
The present invention relates to a multi-phase clock generator, and more particularly, to a multi-phase clock generator which can be controlled by a digital signal.
2. Description of the Related Art
In order to increase an operation speed of an inside of a chip or a communication speed between chips as compared with a frequency of a clock signal that is externally input, a clock having a multi-phase is used. For example a method of increasing a transmission speed by using a number of clocks having a low frequency and serializing data generated from a rising edge of each clock signal is used. When a multi-clock is used, although an operation speed of the inside of the chip is currently 3 GHz, the communication speed between chips of 10 Gb/s or more can be achieved. In order to generate the multi-clock, a phase locked loop (PLL) and a delay locked loop (DLL) are generally used.
A core circuit block for generating clocks having a multi-phase by using the PLL and the DLL is a delay line block.
FIG. 1 is a block diagram for explaining a general DLL.
Referring to FIG. 1, the DLL 100 includes a delay line 110, a phase detector 120, and a charge pump/loop filter 130.
The delay line 110 includes four delay cells for generating four clocks clk90, clk180, clk270, and clk360 having a time interval of 0.25T. Here, T is a period of a clock. The phase detector 120 compares a phase of a clock clk0 with a phase of the clock clk360 and outputs a comparing signal Diff in order to synchronize the phases of the clocks clk0 and clk360. The charge pump 130 changes a control voltage Vcon in response to the comparing signal Diff. A delay time of the delay line 110 is controlled by the changed control voltage Vcon so that the phases of the clocks clk0 and clk360 are synchronized.
FIG. 2 is an operation timing diagram of the DLL in FIG. 1.
Referring to FIG. 2, it is shown that when the DLL 100 is locked, rising edges of the clocks clk0 and clk360 are synchronized, so that the output clocks clk90, clk180, clk270, and clk 360 of the DLL 100 have an interval of 0.25T.
The DLL 100 for generating clocks having a multi-phase has the following problems.
First, time intervals between the clocks clk90, clk180, clk270, and clk360 may change due to mismatches between delay cells disposed inside the delay line 110 or mismatches in paths along which the clocks clk90, clk180, clk270, and clk360 pass. The mismatches between the delay cells mainly occur due to a difference in a size or in a threshold voltage between transistors. In particular, when the operation speed of the clock is increased, a delay time of the delay cell has to be lowered. However, a channel length L of the transistor can be shortened, so that the mismatches may become larger.
Second, minimum time intervals between the clocks clk90, clk180, clk270, and clk360 are restricted by a minimum delay time of the delay cell. More specifically, a clock having a smaller time interval than a delay time of a delay cell cannot be generated.
Accordingly, an increase in the operation speed of the DLL 100 is limited.